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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2006, zarlink semiconductor inc. all rights reserved. zarlink has introduced a new generation family of aec (zl38002 and zl38004). zarlink recommends these products for new designs. features ? contains two echo cancellers: 112 ms acoustic echo canceller + 16 ms line echo canceller ? works with low cost voice codec. itu-t g.711 or signed mag /a-law, or linear 2?s comp ? each port may operate in different format ? advanced nlp design - full duplex speech with no switched loss on audio paths ? fast re-convergence time: tracks changing echo environment quickly ? adaptation algorithm converges even during double-talk ? designed for exceptional performance in high background noise environments ? provides protection against narrow-band signal divergence ? howling prevention stops uncontrolled oscillation in high loop gain conditions ? offset nulling of all pcm channels ? serial micro-controller interface ? st-bus, gci, or variable-rate ssi pcm interfaces ? user gain control provided for speaker path (-24db to +48db in 3db steps) ? 18 db gain at sout to compensate for high erl environments ? agc on speaker path ? handles up to 0 db acoustic echo return loss ? transparent data transfer and mute options ? 20 mhz master clock operation ? low power mode during pcm bypass ? bootloadable for future factory software upgrades ? 2.7 v to 3.6 v supply voltage; 5 v-tolerant inputs october 2006 ordering information zl38001dga 36 pin qsop tubes zl38001qdc 48 pin tqfp trays zl38001qdg1 48 pin tqfp* trays, bake & drypack zl38001dgf1 36 pin ssop* tape & reel, bake & drypack zl38001dge1 36 pin ssop* tubes, bake & drypack *pb free matte tin -40 c to +85 c zl38001 aec for analog hands-free communication data sheet figure 1 - functional block diagram rout md1 md2 port 2 sin line echo path s 1 micro interface program ram program rom format l inear/ /a-law offset null linear /a-law/ linear/ /a-law adaptive filter offset null vdd vss reset f0i bclk/c4i mclk sout rin data1 data2 cs sclk ena2 law agc user gain + - adv + - -24 -> +21 db r 1 r 2 r 3 s 2 s 3 nlp adv nlp linear /a-law/ + + howling controller port 1 nbsd adaptive filter unit control detector talk double nbsd ena1 limiter limiter acoustic echo path 18db gain
zl38001 data sheet 2 zarlink semiconductor inc. applications ? hands-free in automobile applications mt93l16 zl38001 zl38002 zl38003 description aec for analog hands- free communication aec for analog hands- free communication aec with noise reduction for digital hands-free communication aec with noise reduction & codecs for digital hands-free communication application analog desktop phone analog intercom analog desktop phone analog intercom hands-free car kits digital desktop ph one home security intercom & pedestals hands-free car kits digital desktop ph one home security intercom & pedestals features aec 1 channel 1 channel 1 channel 1 channel lec 1 channel 1 channel custom load custom load gains user gain us er gain/18 db gain on sout user gain + system tuning gains user gain + system tuning gains noise reduction nn y y integrated codecs n n n dual channel table 1 - acoustic echo cancellation family
zl38001 data sheet 3 zarlink semiconductor inc. figure 2 - pin connections pin description qsop pin # tqfp pin # name description 143ena1 ssi enable strobe/st-bus & gci mode for rin/sout (input). this pin has dual functions depending on whether ssi or st-bus/gci is selected. for ssi, this strobe must be present fo r frame synchronization. this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer for on rin/sout pins. strobe period is 125 microseconds. for st-bus or gci, this pin, in conjunction with the md1 pin, selects the proper mode for rin/sout pins (see st-bus and gci operation description). 245md1 st-bus & gci mode for rin/sout (input). when in st-bus or gci operation, this pin, in conjunction with the ena1 pin, will select the proper mode for rin/sout pins (see st-b us and gci operation description). connect this pin to vss in ssi mode. 346ena2 ssi enable strobe /st-bus & gci mode for sin/rout (input). this pin has dual functions depending on whether ssi or st-bus/gci is selected. for ssi, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer on si n/rout pins. strobe period is 125 microseconds. for st-bus/gci, this pin, in conjunction with the md2 pin, selects the proper mode for sin/rout pins (see st-bus and gci operation description). 447md2 st-bus & gci mode for sin/rout (input). when in st-bus or gci operation, this pin in conjunction wi th the ena2 pin, selects the proper mode for sin/rout pins (see st-b us and gci operation description). connect this pin to vss in ssi mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 19 20 28 27 26 25 24 23 22 21 data2 vdd nc ic nc data1 sclk sout rout bclk/c4i ic ic sin rin ic md2 md1 f0i format ic law ena1 reset nc ena2 mclk cs qsop 32 31 vss nc 30 29 vss2 vdd2 ic 17 18 33 34 35 36 mclk2 ic ic ic tqfp 34 36 38 40 42 44 46 48 16 14 12 10 8 6 4 2 cs resetb nc nc sout data2 sclk sin ic ic nc ic ic nc law mclk2 ena2 ic ic ic nc nc ic nc 18 20 22 24 26 30 32 28 md2 md1 ena1 nc nc nc bclk/c4i vss vdd2 format f0i rout vss2 nc mclk nc ic nc nc data1 nc vdd nc rin
zl38001 data sheet 4 zarlink semiconductor inc. 548rin receive pcm signal input (input). 128 kbps to 4096 kbps serial pcm input stream. data may be in either companded or 2?s complement linear format. this is the receive input channel from the line (or network) side. data bits are clocked in following ssi , gci or st-bus timing requirements. 62sin send pcm signal input (input). 128 kbps to 4096 kbps serial pcm input stream. data may be in either companded or 2?s complement linear format. this is the send input channel (f rom the microphone). data bits are clocked in following ssi, gci or st-bus timing requirements. 73ic internal connection (input). must be tied to vss. 85mclk master clock (input). nominal 20 mhz master clock input (may be asynchronous relative to 8 khz fram e signal.) tie together with mclk2 (pin 33). 9,10,11 6, 7, 8 ic internal connection (input). must be tied to vss. 12 9 law a/ law select (input). when low, selects ? law companded pcm. when high, selects a-law companded pcm. this control is for both serial pcm ports. 13 11 format itu-t/sign mag (input). when low, selects sign-magnitude pcm code. when high, selects itu-t (g.711) pcm code. this control is for both serial pcm ports. 14 13 reset reset / power-down (input). an active low resets the device and puts the zl38001 into a low-power stand-by mode. 17 16 sclk serial port synchronous clock (input). data clock for the serial microport interface. 18 17 cs serial port chip select (input). enables serial microport interface data transfers. active low. 19 19 data2 serial data receive (input). in motorola/national serial microport operation, the data2 pin is used for re ceiving data. in intel serial microport operation, the data2 pin is not used and must be tied to vss or vdd. 20 21 data1 serial data port (bidirectional). in motorola/national serial microport operation, the data1 pin is used for transmitting data. in intel serial microport operation, the data1 pin is used for transmitting and receiving data. 22 23 vdd positive power supply (input ). nominally 3.3 volts. 23 24 sout send pcm signal output (output). 128 kbps to 4096 kbps serial pcm output stream. data may be in either companded or 2?s complement linear pcm format. this is the send out signal after acoustic echo cancellation and non-linear processing. data bits are clocked out following ssi, st- bus or gci timing requirements. 24 26 rout receive pcm signal output (output). 128 kbps to 4096 kbps serial pcm output stream. data may be in either companded or 2?s complement linear pcm format. this is the receive out signal after line echo cancellation non- linear processing, agc and gain contro l. data bits are clocked out following ssi, st-bus or gci timing requirements. pin description (continued) qsop pin # tqfp pin # name description
zl38001 data sheet 5 zarlink semiconductor inc. 25 27 f0i frame pulse (input). in st-bus (or gci) operation, this is an active-low (or active-high) frame alignment pul se, respectively. ssi operation is enabled by connecting this pin to vss. 26 29 bclk/c4i bit clock/st-bus clock (input). in ssi operation, bclk pin is a 128 khz to 4.096 mhz bit clock. this clock must be synchronous with ena1 and ena2 enable strobes. in st-bus or gci operation, c4i pin must be connected to the 4.096 mhz (c4 ) system clock. 27, 28 30, 31 ic internal connection (input). tie to vss. 29 33 vss2 digital ground (input). nominally 0 volts. 30 34 vdd2 positive power supply (input). nominally 3.3 volts (tie together with vdd, pin 22). 31 35 vss digital ground (input). nominally 0 volts (tie together with vss2, pin 29). 33 38 mclk2 master clock (input). nominal 20 mhz master clock (tie together with mclk, pin 8). 34,35,36 39, 40, 41 ic internal connection (input). tie to vss. 15, 16, 21, 32 1, 4, 10, 12, 14, 15, 18, 20, 22, 25, 28, 32, 36, 37, 42, 44 nc no connect (output). this pin should be left unconnected. pin description (continued) qsop pin # tqfp pin # name description
zl38001 data sheet table of contents 6 zarlink semiconductor inc. 1.0 changes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 adaptation speed control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 advanced non-linear processor (adv-nlp)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 narrow band signal detector (nbsd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 howling detector (hwld)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 offset null filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 user gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 agc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 18 db gain pad at sout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.10 mute function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.11 bypass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.12 adaptation enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.13 zl38001 throughput delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.14 power down / reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.0 pcm data i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 st-bus and gci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 ssi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 pcm law and format control (law, format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 linear pcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 bit clock (bclk/c4i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 master clock (mclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 bootload process and execution from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
zl38001 data sheet list of figures 7 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3 - st-bus and gci 8-bit companded pcm i/o on timeslot 0 (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 - st-bus and gci 8-bit companded pcm i/o on timeslot 2 (mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5 - st-bus and gci 8-bit companded pcm i/o with d and c channels (mode 3) . . . . . . . . . . . . . . . . . . 16 figure 6 - st-bus and gci 16-bit 2?s complement linear pcm i/o (mode 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7 - ssi operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8 - serial microport timing for intel mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9 - serial microport timing for motorola mode 00 or national microwire . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10 - master clock - mclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11 - gci data port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12 - st-bus data port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13 - ssi data port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14 - intel serial microport timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15 - motorola serial microport timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
zl38001 data sheet list of tables 8 zarlink semiconductor inc. table 1 - acoustic echo cancellation family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2 - quiet pcm code assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 - st-bus & gci mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4 - ssi enable strobe pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5 - companded pcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6 - bootload ram control (brc) register states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7 - reference level definition for timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
zl38001 data sheet list of register tables 9 zarlink semiconductor inc. register table 1 - main control register (mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 register table 2 - acoustic echo canceller control register (aec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 register table 3 - line echo canceller control register (lec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 register table 4 - acoustic echo c anceller status register (asr) (* do not write to this register) . . . . . . . . . . . . . . . . . 32 register table 5 - line echo canceller status register (lsr) (* do not write to this register) . . . . . . . . . . . . . . . . . . . . . 33 register table 6 - receive gain control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 register table 7 - double talk gain control register 1 (dtgcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 register table 8 - double talk gain control register 2 (dtgcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 register table 9 - double talk detection threshold register (dtdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 register table 10 - receive (rin) peak detect register 1 (rip d1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 register table 11 - receive (rin) peak detect register 2 (ripd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 register table 12 - receive (rin) error peak detect register 1 (repd1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 register table 13 - receive (rin) error peak detect register 2 (repd2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 register table 14 - receive (rout) peak detect register 1 (ropd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 register table 15 - receive (rout) peak detect register 2 (ropd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 register table 16 - send (sin) peak detect register 1 (sipd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 register table 17 - send (sin) peak detect register 2 (sipd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 register table 18 - send error peak detect register 1 (sepd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 register table 19 - send error peak detect register 2 (sepd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 register table 20 - send (sout) peak detect register 1 (sopd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 register table 21 - send (sout) peak detect register 2 (sopd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 register table 22 - rout limiter register 1 (rl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 register table 23 - rout limiter register 2 (rl2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 register table 24 - sout limiter register (sl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 register table 25 - firmware revision code register (frc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 register table 26 - bootload ram control register (brc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 register table 27 - bootload ram signature r egister (sig) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
zl38001 data sheet 10 zarlink semiconductor inc. 1.0 changes summary the following table captures the changes from the november 2005 issue. the following table captures the changes from the june 2004 issue. 2.0 functional description the zl38001 device contains an acoustic echo cancellers , as well as the many control functions necessary to operate the echo canceller. the zl38001 provides clear si gnal transmission in both audio path directions to ensure reliable voice communication, even with low level signals . the zl38001 does not use variable attenuators during double-talk or single-talk periods of speech, as do ma ny other acoustic echo cancellers for speakerphones. instead, the zl38001 provides high performance full-duplex operation similar to network echo cancellers, so that users experience clear speech and uninterrupted background signals duri ng the conversation. this prevents subjective sound quality problems associated wi th ?noise gating? or ?noise contrasting?. the zl38001 uses an advanced adaptive filt er algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking 1 . this algorithm allows continual tracking of changes in the echo path, regardless of double-talk, as long as a refe rence signal is available for the echo canceller. the echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112 ms) to cancel echo in an average sized office with a reverberation time of less than 112 ms. in addition to the echo cancellers, the following functions are supported: ? control of adaptive filter convergence speed during periods of double-talk, far end single-talk and near-end echo path changes ? control of non-linear processor thresholds for suppression of residual non-linear echo ? howling detector to identify when instability is starti ng to occur and to take action to prevent oscillation ? narrow-band detector for preventing adaptive fi lter divergence caused by narrow-band signals ? offset nulling filters for removal of dc components in pcm channels ? limiters that introduce controlled saturation levels ? serial controller interface compatible with motorola, national and intel microcontrollers ? pcm encoder/decoder compatible with /a-law itu-t g.711, /a-law sign-mag or linear 2?s complement coding ? automatic gain control on the receive speaker path page item change 1 updated ordering information page item change 1 features added 16 ms line echo canceller. 1 figure 1 - functional block diagram added line echo cancellor block. 1. patent pending.
zl38001 data sheet 11 zarlink semiconductor inc. 2.1 adaptation speed control the adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. adap tation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change and noise levels to achieve fast convergence. 2.2 advanced non-li near processor (adv-nlp) 1 after echo cancellation, there is likely to be residual ec ho which needs to be removed so that it will not be audible. the zl38001 uses an nlp to remove low level residual ec ho signals which are not comprised of background noise. the operation of the nlp depends upon a dynamic activation threshold, as well as a double-talk detector which disables the nlp duri ng double-talk periods. the zl38001 keeps the perceived noise level constant, wi thout the need for any variable attenuators or gain switching that causes audibl e ?noise gating?. the noise level is consta nt and identical to the original background noise even when the nlp is activated. the nlp can be disabled by setting the nlp- bit to 1 in the aec control registers. 2.3 narrow band signal detect or (nbsd) 1 single or multi-frequency tones (e.g., dtmf or signalling tones) present in the referenc e input of an echo canceller for a prolonged period of time may cause the adaptive filt er to diverge. the narrow band signal detector (nbsd) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. when narrow band signals are detected, the filter adaptat ion process is stopped but the echo canceller continues to cancel echo. the nbsd can be disabled by setting the nb - bit to 1 in the mc control registers. 2.4 howling detector (hwld) 1 the howling detector is part of an anti-howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. the hwld can be disabled by setting the ah- bit to 1 in the (mc) control register. 2.5 offset null filter to ensure robust performance of the adapti ve filters at all times, any dc offset that may be present on either the rin signal or the sin signal, is removed by highpass filter s. these filters have a corner frequency placed at 40 hz. the offset null filters can be di sabled by setting the hpf- bit to 1 in the aec control registers. 2.6 limiters to prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs. the rout limiter threshold is in rout li miter register 1 and 2. the sout limiter threshold is in sout limiter register. both output limiters are always enabled. 2.7 user gain the user gain function prov ides the ability for users to adjust the audio gain in the receive path (speaker path). this gain is adjustable from -24 db to +48 db in 3 db steps. it is important to use only this user gain function to adjust 1. patent pending
zl38001 data sheet 12 zarlink semiconductor inc. the speaker volume. the user gain function in the zl3800 1 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes. the gain can be accessed through receive gain control register. 2.8 agc the agc function is provided to limit the volume in the s peaker path. the gain of the speaker path is automatically reduced during the fo llowing conditions: ? when clipping of the receive signal occurs ? when initial convergence of the acoustic echo canceller detects unusually large echo return ? when howling is detected ? the agc can be disabled by setting the agc- bit to 1 in mc control register 2.9 18 db gain pad at sout the purpose of the 18 db gain pad is to improve the subj ective quality in low erl environments. the zl38001 can cancel echo with a erl as low as 0 db (attenuation from rout to sin). in many hand free applications, the erl can be low (or negative). this is due to both speaker and microphone gain setting. the speaker gain has to be set high enough for the speaker to be heard properly and the mi crophone gain needs to be set high enough to ensure sufficient signal is sent to the far end. if the erl (ac oustic attenuation - speaker gain - microphone gain) is greater than 0 db, then the echo canceller cannot cancel echo. to overcome this limitation, the zl38001 has a 18 db gain pad at sout. the microphone gain can be reduced by 18 db to allow either the speaker gain and/or the acoustic coupling to be increased by a total of 18 db allowing more flexibility in the design. 2.10 mute function a pcm mute function is provided for independent control of the receive and send audio paths. setting the mute_r or mute_s bit in the mc register, causes quiet code to be transmitted on the rout or sout paths respectively. quiet code is defined according to the following table. linear 16 bits 2?s complement sign/ magnitude -law a-law ccitt (g.711) -law a-law +zero (quiet code) 0000h 80h ffh d5h table 2 - quiet pcm code assignment
zl38001 data sheet 13 zarlink semiconductor inc. 2.11 bypass control a pcm bypass function is provided to allow transparent transmission of pcm data through the zl38001. when the bypass function is active, pcm data passes transparently from rin to rout and from sin to sout, with bit-wise integrity preserved. when the bypass function is selected, most inter nal functions are powered down to provide low power consumption. the bypass control bit is located in the main control mc register. 2.12 adaptation enable/disable adaptation control bits are located in the aec and lec c ontrol registers. when the adapt- bit is set to 1, the adaptive filter is frozen at th e current state. in this state, the device co ntinues to cancel echo with the current echo model. when the adapt- bit is set to 0, the adaptive filter is continually updated. this allows the echo canceller to adapt and track changes in the echo path. this is the normal operating state. 2.13 zl38001 throughput delay in all modes, voice channels always have 2 frames of delay. in st-bus/gci operation, the d and c channels have a delay of one frame. 2.14 power down / reset holding the reset pin at logic low will keep the zl38001 device in a power-down state. in this state all internal clocks are halted, and the data1, sout and rout pins are tristated. the user should hold the reset pin low for at least 200 msec following po wer-up. this will insure that the device powers up in a proper state. following any return of reset to logic high, the user must wait for 8 complete 8 khz frames prior to writing to the device registers. during this time, the initialization routines will execute and set the zl38001 to default operation (program executi on from rom using defaul t register values).
zl38001 data sheet 14 zarlink semiconductor inc. 3.0 pcm data i/o the pcm data transfer for the zl38001 is provided through two pcm ports. one port consists of rin and sout pins while the second port consists of si n and rout pins. the data are transfe rred through these ports according to either st-bus, gci or ssi conventions and the device automatically det ects the correct convention. the device determines the convention by monito ring the signal applied to the f0i pin. when a valid st-bus (active low) frame pulse is applied to the f0i pin, the zl38001 will assume st-bus operation. when a valid gci (active high) frame pulse is applied to the f0i pin, the device will as sume gci operation. if f0i is tied continuously to vss, the device will assume ssi operatio n. figures 11 to 13 show ti ming diagrams of thes e 3 pcm-interface oper ation conventions. 3.1 st-bus and gci operation the st-bus pcm interface conforms to zarlink?s st-bus standard with an active-low frame pulse. input data is clocked in by the rising edge of the bit clock (c4i ) three-quarters of the way into the bitcell and output data bit boundaries (rout, sout) occur every second falling edge of the bit clock (see figure 11.) the gci pcm interface corresponds to the gci standard commonly used in europe with an active-high frame pulse. input data is clocked in by the falling edge of the bit clock (c4i ) three-quarters of the way into the bitcell and output data bit boundaries (rout, sout) occur every second rising edge of the bit clock (see figure 12.) either of these interfaces (stbus or gci) can be used to transport 8 bit companded pcm data (using one timeslot) or 16 bit 2?s complement linear pcm data (using two time slots). the md1/ena1 pins select the timeslot on the rin/sout port while the md2/ena2 pin se lects the timeslot on the sin/rout por t, as in table 3. figures 3 to 6 illustrate the timeslot allocation for each of these four modes. figure 3 - st-bus and gci 8-bit companded pcm i/o on timeslot 0 (mode 1) c4i f0i (st-bus) sin rout rin sout 76 543 210 76 543 210 76543 210 76543 210 outputs = high impedance inputs = don?t care in st-bus/gci mode 1, echo canceller i/o channels are assigned to st-bus/gci timeslot 0. note that the user can configure port1 and port2 into different modes. port1 port2 01 2 34 b f0i (gci) start of frame (stbus & gci) ec ec
zl38001 data sheet 15 zarlink semiconductor inc. figure 4 - st-bus and gci 8-bit companded pcm i/o on timeslot 2 (mode 2) c4i f0i (st-bus) sin rout rin sout 76543 21 0 76543 21 0 76 543 210 76543 21 0 in st-bus/gci mode 2, echo canceller i/o channels are assigned to st-bus/gci timeslot 2. note that the user can configure port1 and port2 into different modes. port1 port2 01 2 34 outputs = high impedance inputs = don?t care b f0i (gci) start of frame (stbus & gci) ec ec
zl38001 data sheet 16 zarlink semiconductor inc. figure 5 - st-bus and gci 8-bit companded pcm i/o with d and c channels (mode 3) c4i f0i (st-bus) rin sout ec sin rout ec port1 port2 indicates that an input channel is bypassed to an output channel st-bus/gci mode 3 supports connection to 2 b+d devices where timeslots 0 and 1 transport d and c channels and echo canceller (ec) i/o channels are assigned to st-bus timeslot 2 (b). both port1 and port2 must be configured in mode 3. 01 2 34 outputs = high impedance inputs = don?t care 76 543 21 0 76 54 321 0 76 54 321 0 76 543 210 76 543 21 0 76 54 321 0 76 54 321 0 76 543 210 76 543 21 0 76 54 321 0 76 54 321 0 76 543 210 d c b f0i (gci) start of frame (stbus & gci)
zl38001 data sheet 17 zarlink semiconductor inc. figure 6 - st-bus and gci 16-bit 2?s complement linear pcm i/o (mode 4) 3.2 ssi operation the ssi pcm interface consists of data input pins (rin, sin) , data output pins (sout, rout ), a variable rate bit clock (bclk), and two enable pins (ena1, ena2) to provide stro bes for data transfers. the active high enable may be either 8 or 16 bclk cycles in durat ion. automatic detection of the data type (8 bit companded or 16-bit 2?s complement linear) is accomplished internally. the data type cannot change dynamically from one frame to the next. port1 rin/sout st-bus/gci mode selection port2 sin/rout enable pins enable pins md1 ena1 md2 ena2 0 0 mode 1 . 8 bit companded pcm i/o on timeslot 0 0 0 0 1 mode 2 . 8 bit companded pcm i/o on timeslot 2. 0 1 1 0 mode 3 . 8 bit companded pcm i/o on timeslot 2. includes d & c channel bypass in timeslots 0 & 1. 10 1 1 mode 4 . 16-bit 2?s complement linear pcm i/o on timeslots 0 & 1. 11 table 3 - st-bus & gci mode select c4i f0i (stbus) rin sout 76543210 sin rout port1 port2 s14 13 12 111098 st-bus/gci mode 4 allows 16 bit 2?s complement linear data to be transferred using st-bus/gci i/o timing. note that port1 and port2 need not necessarily both be in mode 4. outputs = high impedance inputs = don?t care 76543210 s14 13 12 11 10 9 8 76543210 s14 13 12 11 10 9 8 76543210 s14 13 12 11 10 9 8 f0i (gci) start of frame (stbus & gci) ec ec
zl38001 data sheet 18 zarlink semiconductor inc. in ssi operation, the frame boundary is determined by the rising edge of the ena1 enable strobe (see figure 7). the other enable strobe (ena2) is used for parsing inpu t/output data and it must pulse within 125 microseconds of the rising edge of ena1. in ssi operation, the enable st robes may be a mixed combination of 8 or 16 bclk cycles allowing the flexibility to mix 2?s complement linear data on one port (e.g., rin/sout ) with companded data on the other port (e.g., sin/rout). table 4 - ssi enable strobe pins 3.3 pcm law and format control (law, format) the pcm companding/coding law used by the zl38001 is controlled through the law and format pins. itu-t g.711 companding curves for -law and a-law are selected by the law pin. pcm coding itu-t g.711 and sign- magnitude are selected by the format pin. see table 5. figure 7 - ssi operations enable strobe pin designated pcm i/o port ena1 line side echo path (port 1) ena2 acoustic side echo path (port 2) bclk ena1 rin sout 8 or 16 bits 8 or 16 bits port1 port2 8 or 16 bits 8 or 16 bits ena2 sin rout note that the two ports are independent so that, for example, port1 can operate with 8-bit enable strobes and port2 can operate with 16-bit enable strobes. outputs = high impedance inputs = don?t care start of frame (ssi) ec ec
zl38001 data sheet 19 zarlink semiconductor inc. 3.4 linear pcm the 16-bit 2?s complement pcm linear coding permits a dynamic range beyond that which is specified in itu-t g.711 for companded pcm. the echo-cancellation algorithm wi ll accept 16-bits 2?s complement linear code which gives a maximum signal level of +15 dbm0. 3.5 bit clock (bclk/c4i ) the bclk/c4i pin is used to clock the pcm data for gci and st-bus (c4i ) interfaces, as well as for the ssi (bclk) interface. in ssi operation, the bit rate is determined by the bclk frequency. this i nput must contain either eight or sixteen clock cycles within the valid enable strobe window. bc lk may be any rate between 128 khz to 4.096 mhz and can be discontinuous outside of the enable strobe windows defined by ena1, ena2 pins. incoming pcm data (rin, sin) are sampled on the falling edge of bclk while outgoing pcm data (sout, rout) are clocked out on the rising edge of bclk. see figure 13. in st-bus and gci operation, connect the system c4 (4.096 mhz) clock to the c4i pin. 3.6 master clock (mclk) a nominal 20 mhz, continuously-running master clock (mcl k) is required. mclk may be asynchronous with the 8khz frame. 4.0 microport the serial microport provides access to all zl38001 intern al read and write regi sters, plus write- only access to the bootloadable program ram (see next section for bootload de scription.) this microport is compatible with intel mcs-51 (mode 0), motorola spi (cpol=0, cpha=0) and national semiconductor micr owire specifications. the microport consists of a transmit/receive data pin (data1 ), a receive data pin (data2), a chip select pin (cs ) and a synchronous data clock pin (sclk). the zl38001 automatically adjusts its internal timing and pi n configuration to conform to intel or motorola/national requirements. the microport dynamically senses the state of the sclk pin each time cs pin becomes active (i.e., high to low transition). if sclk pin is high during cs activation, then intel mode 0 timing is assumed. in this case data1 pin is defined as a bi-directiona l (transmit/receive) serial port and data2 is internally disconnected. if sclk is low during cs activation, then motorola/national timing is assu med and data1 is defined as the data transmit pin while data2 becomes the data receive pin. the zl38001 supports motorola half-duplex processor mode (cpol=0 pcm code sign-magnitude format=0 itu-t (g.711) format=1 /a-law law = 0 or 1 -law law = 0 a-law law =1 + full scale 1111 1111 1000 0000 1010 1010 + zero 1000 0000 1111 1111 1101 0101 - zero 0000 0000 0111 1111 0101 0101 - full scale 0111 1111 0000 0000 0010 1010 table 5 - companded pcm
zl38001 data sheet 20 zarlink semiconductor inc. and cpha=0). this means that during a write to the zl 38001, by the motorola processor, output data from the data1 pin must be ignored. this also means that input data on the data2 pin is ignored by the zl38001 during a valid read by the motorola processor. all data transfers through the microport are two bytes l ong. this requires the transm ission of a command/address byte followed by the data byte to be written to or read from the addressed register. cs must remain low for the duration of this two-byte transfer. as shown in figures 8 and 9, the falling edge of cs indicates to the zl38001 that a microport transfer is about to begin. the first 8 clock cycl es of sclk after the falli ng edge of cs are always used to receive the command/address byte from the microcont roller. the command/address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. the next 8 clock cycles are used to transfer the data byte between the zl 38001 and the microcontroller. at the end of the two-byte transfer, cs is brought high again to terminate the session. the rising edge of cs will tri-state the data1 pin. the data1 pin will remain tri-stated as long as cs is high. intel processors utilize least significant bit (lsb) first transmission while motorola/national processors use most significant bit (msb) first transmission. the zl38001 microport automatically accommodates these two schemes for normal data bytes. however, to ensure timely decoding of the r/w and address information, the command/address byte is defined differently for intel and motorola/national operations. refer to the relative timing diagrams of figure 8 and figure 9. rece ive data bits are sampled on the rising edge of sclk while transmit data is clocked out on the falling edge of sclk. detailed micr oport timing is shown in figure 14 and figure 15. 4.1 bootload process and execution from ram a bootloadable program ram (bram) is available on the zl38001 to support factory-issued software upgrades to the built-in algorithm. to make use of this bootload feat ure, users must include 4096 x 8 bits of memory in their microcontroller system (i.e., external to the zl38001), from which the zl38001 can be bootloaded. registers and program data are loaded into the zl38001 in the same fa shion via the serial micropor t. both employ the same command / address / data byte specification described in the previous section on serial microport. either intel or motorola mode may be transparently used for bootloading. there are also two register s relevant to bootloading (brc=control and sig=signature, see register summary). th e effect of these register values on device operation is summarized in table 6. bootload mode is entered and exited by writing to the boo tload bit in the bootload ram control (brc) register at address 3fh (see register summa ry). during bootload mode, any serial microport "write" (r/w command bit =0) to an address other than that of the brc r egister will contribute to filling t he program bram. call these transactions "bram-fill" writes. although a command /address byte must still precede each dat a byte (as descri bed for th e serial microport), the values of the address fi elds for these "bram-fill" writes are ignored (except for the value 3fh, which designates the brc register.) instead, addresses are internally generated by the zl38001 for each "bram-fill" write. address generation for "bram-fill" writes resumes where it left off following any read transaction while bootload mode is enabled. the first 4096 such "bram-fill" writes while bootload is enabled will load the memory, but further ones after that are ignore d. following the write of the first 4096 bytes, the program bram will be filled. before bootload mode is disabled , it is recommended that users then re ad back the value from the signature register (sig) and compare it to the one supplied by the factory along with the code. equality verifies that the correct data has been loaded. the signature calculation uses an 8-bit misr which only incorporates input from "bram-fill" writes. re setting the bootload bit ( c 2 ) in the brc register to 0 (see register summary) exits bootload mode, resetting the signature (sig) register and internal address generator for the next bootload. a hardware reset (reset =0) similarly returns the zl38001 to the re ady state for the start of a bootload.
zl38001 data sheet 21 zarlink semiconductor inc. note: bits c 1 c 0 are reserved, and must be set to zero. functional description for using the bootable ram bootload mode - microport access is to bootload ram (bram) brc register bits c 3 c 2 c 1 c 0 x 1 0 0 r/w address data w3fh (= 1 1 1 1 1 1 b) writes "data" to brc reg. - bootload frozen; bram c ontents are not affected. w other than 3fh writes "data" to next byte in bram (bootloading.) r 1 x x x x x b reads back "data" = brc reg value. - bootload frozen; bram c ontents are not affected. r 0 x x x x x b reads back "data" = sig reg value. - bootload frozen; bram c ontents are not affected. non-bootload mode - microport access is to device registers (dregs) brc register bits c 3 c 2 c 1 c 0 x 0 0 0 r/w address data w any (= a 5 a 4 a 3 a 2 a 1 a 0 b) writes "data" to corresponding dreg. r any (= a 5 a 4 a 3 a 2 a 1 a 0 b) reads back "data" = corresponding dreg value. program execution modes c 3 c 2 c 1 c 0 0 0 0 0 execute program in rom, bootload mode disabled. - bram address counter reset to initial (ready) state. - sig reg reseeded to initial (ready) state c 3 c 2 c 1 c 0 0 1 0 0 execute program in rom, while bootloading the ram. - bram address counter increments on microport writes (except to 3fh) - sig reg recalculates signature on microport writes (except to 3fh) c 3 c 2 c 1 c 0 1 0 0 0 execute program in ram, bootload mode disabled. - bram address counter reset to initial (ready) state. - sig reg reseeded to initial (ready) state c 3 c 2 c 1 c 0 1 1 0 0 - not recommended - (execute program in ram, while bootloading the ram) table 6 - bootload ram control (brc) register states
zl38001 data sheet 22 zarlink semiconductor inc. once the program has been loaded, to begin execution from ram, bootload mode must be disabled (boot bit, c 2 =0) and execution from ram enabled (ram_romb bit, c 3 =1) by setting the appropriate bits in the brc register. during the bootload process, however, rom program execution (ram_romb bit, c 3 =0) should be selected. see table 6 for the effect of the brc register setti ngs on microport accesses and on program execution. following program loading and enabling of execution from ram, it is re commended that users set the software reset bit in the main control (mc) register, to ensure that the device updates the default register values to those of the new program in ram. note: it is important to use a software reset rather than a hardware (reset =0) reset, as the latter will return the device to its default settings (w hich includes execution from program rom instead of ram.) to verify which code revision is currently running, us ers can access the firmware revision code (frc) register (see register summary). this register reflects the identi ty code (revision number) of the last program to run register initialization (which follows a software or hardware reset.) figure 8 - serial microport timing for intel mode 0 r/w a 0 a 1 a 2 a 3 a 4 a 5 x command/address data input/output data 1 sclk cs a b c d e a b c d e this delay is due to internal processor timing and is equal to tsch time. the delay is transparent to zl38001. the zl38001: outputs transmit data on the falling edge of sclk the falling edge of cs indicates that a command/address byte will be tran smitted from the microp rocessor. t he subsequent byte is always data followed by cs returning high. a new command/address byte ma y be loaded only by cs cycling high then low again. the command/address byte c ontains: 1 bit - read/write 6 bits - addressing data 1 bit - unused d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 latches receive data on the rising edge of sclk
zl38001 data sheet 23 zarlink semiconductor inc. figure 9 - serial microport timing for motorola mode 00 or national microwire x a 0 a 1 a 2 a 3 a 4 a 5 r/w command/address data input data 2 receive data 1 transmit sclk cs a b c d e a c d e this delay is due to internal processor timing and is equal to tsch time. the delay is transparent to zl38001. the falling edge of cs indicates that a command/address byte will be tran smitted from the microp rocessor. t he subsequent byte is always data followed by cs returning high. a new command/address byte ma y be loaded only by cs cycling high then low again. the command/address byte c ontains: 1 bit - read/write 6 bits - addressing data 1 bit - unused d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 high impedance data output b the zl38001: outputs transmit data on the falling edge of sclk latches receive data on the rising edge of sclk
zl38001 data sheet 24 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. *dc electrical characteristics are over recommended temperature and supply voltage. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd -v ss -0.5 5.0 v 2 input voltage v i v ss -0.3 5.5 v 3 output voltage swing v o v ss -0.3 5.5 v 4 continuous current on any digital pin i i/o 20 ma 5 storage temperature t st -65 150 c 6 package power dissipation p d 90 (typ) mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. max. units test conditions 1 supply voltage v dd 2.7 3.3 3.6 v 2 input high voltage 1.4 v dd v 3 input low voltage v ss 0.4 v 4 operating temperature t a -40 +85 c echo return limits characteristics min. typ. max. units test conditions 1 acoustic echo return 0 db measured from rout -> sin 2 line echo return 0 db measured from sout -> rin dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units conditions/notes 1 standby supply current: i cc 370 a reset = 0 operating supply current: i dd 20 ma reset = 1, clocks active 2 input high voltage v ih 0.7v dd v 3 input low voltage v il 0.3v dd v 4 input leakage current i ih /i il 0.1 10 av in =v ss to v dd 5 high level output voltage v oh 0.8 v dd vi oh =2.5 ma 6 low level output voltage v ol 0.4v dd vi ol =5.0 ma 7 high impedance leakage i oz 110 av in =v ss to v dd 8 output capacitance c o 10 pf 9 input capacitance c i 8pf
zl38001 data sheet 25 zarlink semiconductor inc. ? timing is over recommended temperature and power supply voltages. ac electrical characteristics ? - serial data interfaces - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. max. units test notes 1 mclk frequency f clk 19.15 20.5 mhz 2 bclk/c4i clock high t bch, t c4h 90 ns 3 bclk/c4i clock low t bll, t c4l 90 ns 4 bclk/c4i period t bcp 240 7900 ns 5 ssi enable strobe to data delay (first bit) t sd 80 ns c l = 150 pf 6 ssi data output delay (excluding first bit) t dd 80 ns c l = 150 pf 7 ssi output active to high impedance t ahz 80 ns c l = 150 pf 8 ssi enable strobe signal setup t sss 10 t bcp -15 ns 9 ssi enable strobe signal hold t ssh 15 t bcp -10 ns 10 ssi data input setup t dis 10 ns 11 ssi data input hold t dih 15 ns 12 st-bus/gci f0i setup t f0is 20 150 ns 13 st-bus/gci f0i hold t f0ih 20 150 ns 14 st-bus/gci data output delay t dsd 80 ns c l = 150 pf 15 st-bus/gci output active to high impedance t ashz 80 ns c l = 150 pf 16 st-bus/gci data input hold time t dsh 20 ns 17 st-bus/gci data input setup time t dss 20 ns
zl38001 data sheet 26 zarlink semiconductor inc. ? timing is over recommended temperature range and recommended power supply voltages. figure 10 - master clock - mclk ac electrical characteristics ? - microport timing characteristics sym. min. typ. max. units test notes 1 input data setup t ids 30 ns 2 input data hold t idh 30 ns 3 output data delay t odd 100 ns c l = 150 pf 4 serial clock period t scp 500 ns 5 sclk pulse width high t sch 250 ns 6 sclk pulse width low t scl 250 ns 7 cs setup-intel t cssi 200 ns 8cs setup-motorola t cssm 100 ns 9cs hold t csh 100 ns 10 cs to output high impedance t ohz 100 ns c l = 150 pf characteristic symbol cmos level units cmos reference level v ct 0.5*v dd v input high level v h 0.9*v dd v input low level v l 0.1*v dd v rise/fall high measurement point v hm 0.7*v dd v rise/fall low measurement point v lm 0.3*v dd v table 7 - reference level definition for timing measurements mclk (i) v h v l v ct t=1/f clk notes: o. cmos output i. cmos input (5 v tolerant) (see table 8 for symbol definitions)
zl38001 data sheet 27 zarlink semiconductor inc. figure 11 - gci data port timing figure 12 - st-bus data port timing sout/rout (o) v ct c4i (i) v h v l v ct f0i (i) v h v l v ct rin/sin (i) v h v l v ct t f0is t f0ih t dss t dsh t dsd t ashz t c4h t c4l bit 6 bit 7 bit 6 start of frame input sampled bit 7 sout/rout (o) v ct c4i (i) v h v l v ct f0i (i) v h v l v ct rin/sin (i) v h v l v ct t f0is t f0ih t dss t dsh t dsd t ashz t c4h t c4l bit 7 bit 6 bit 6 start of frame input sampled bit 7
zl38001 data sheet 28 zarlink semiconductor inc. figure 13 - ssi data port timing figure 14 - intel serial microport timing sout/rout (o) v ct bclk (i) v h v l v ct ena1 (i) v h v l v ct rin/sin (1) v h v l v ct t sd t sss t dd t ahz t ssh t dis t dih t bcp t bch t bcl bit 7 bit 6 or ena2 (i) input sampled start of frame bit 5 bit 7 bit 6 bit 5 notes: o. cmos output i. cmos input (5 v tolerant) (see table 8 for symbol definitions) data1 (i,o) v ct sclk (i) v h v l v ct cs ( i) v h v l v ct t ids t idh t odd t ohz t cssi t csh t scl t sch t scp data input data output notes: o. cmos output i. cmos input (5 v tolerant) (see table 8 for symbol definitions)
zl38001 data sheet 29 zarlink semiconductor inc. figure 15 - motorola serial microport timing data2 (i) v h v l v ct sclk (i) v h v l v ct cs (i) v h v l v ct data1 (o) v ct t ids t idh t odd t cssm t csh t ohz t sch t scl t scp (input) (output) notes: o. cmos output i. cmos input (5 v tolerant) (see table 8 for symbol definitions)
zl38001 data sheet 30 zarlink semiconductor inc. 5.0 register summary bit name description 7 limit when high, the 2-bit shift mode is enabled in conjunction with bit 7 of lec register and when low 2-bit shift mode is disabled. default limit for rin and sin is 3.14 dbm0. 6 mute_r when high, the rin path is muted to quite code (after the nlp) and when low the rin path is not muted. 5 mute_s when high, the sin path is muted to quite code (after the nlp) and when low the sin path is not muted. 4 bypass when high, the send and receive pa ths are transparently by-passed from input to output and when low the send and receive paths are not bypassed. 3 nb- when high, narrowband signal detectors in rin and sin paths are disabled and when low the signal detectors are enabled. 2 agc- when high, agc is disabled and when low agc is enabled. 1 ah- when high, the howling detector is disabled and when low the howling detector is enabled. 0 reset when high, the power initialization ro utine is executed pres etting all registers to default values. this bit automatically clears itself to ?0? when reset is complete. register table 1 - main control register (mc) bit name description 7 p- when high, the exponential weighting function for the adaptive filter is disabled and when low the we ighting function is enabled 6 asc- when high, the internal adaptation speed control is disabled and when low the adaptation speed is enabled. 5 nlp- when high, the non linear processor is disabled in the sin/sout path and when low the nlp is enabled. register table 2 - acoustic echo canceller control register (aec) external read/write address: 00 h reset value: 00 h 76543210 limit mute_r mute_s bypass nb- agc- ah- reset external read/write address:21 h reset value: 00 h 76543210 p- asc- nlp- inj- hpf- hclr adapt- ecby
zl38001 data sheet 31 zarlink semiconductor inc. 4 inj- when high, the noise filtering process is disabled in the nlp and when low the noise filtering process is enabled. 3 hpf- when high, offset nulling filter is bypassed in the sin/sout path and when low the offset nulling filter in not bypassed. 2 hclr when high, adaptive filter coeffici ents are cleared and when low the filter coefficients are not cleared 1 adapt- when high, the echo canceller adaptation is disabled and when low the adaptation is enabled. 0 ecby when high, the echo estimate from t he filter is not subtracted from the input (sin), when low the estimate is subtracted. bit name description 7 shft when high the 16-bit linear mode, input s sin, rin, are shift right by 2 and outputs sout, rout are shift left by 2. this bit is ignored when 16-bit linear mode is not selected in both ports. this bit is also ignored if bit 7 of mc register is set to zero. 6 asc- when high, the internal adaptation speed control is disabled and when low the adaptation speed is enabled. 5 nlp- when high, the non linear processor is disabled in the rin/rout path and when low the nlp is enabled. 4 inj- when high, the noise filtering process is disabled in the nlp and when low the noise filtering process is enabled. 3 hpf- when high, offset nulling filter is bypassed in the rin/rout path and when low the offset nulling filter in not bypassed. 2 hclr when high, adaptive filter coeffici ents are cleared and when low the filter coefficients are not cleared. register table 3 - line echo canceller control register (lec) bit name description register table 2 - acoustic echo cancel ler control register (aec) (continued) external read/write address:21 h reset value: 00 h 76543210 p- asc- nlp- inj- hpf- hclr adapt- ecby external read/write address: 01 h reset value: 00 h 76543210 shft asc- nlp- inj- hpf- hclr adapt- ecby
zl38001 data sheet 32 zarlink semiconductor inc. register table 4 - acoustic echo ca nceller status register (asr) (* do not write to this register) 1 adapt- when high, the echo canceller adaptation is disabled and when low the adaptation is enabled. 0 ecby when high, the echo estimate from the filter is not substr acted from the input (rin), when low the estimate is substracted. bit name description 7 - reserved. 6 acmund when low, no active signal in the rin/rout path. 5 hwlng when high, howling is occurring in the loop and when low, no howling is detected. 4 - reserved. 3 nlpdc when high, the nlp is activated and when low the nlp is not activated. 2 dt when high the double talk is detected and when low, the double talk is not detected. 1 nb logical or of the status bi t nbs + nbr from lsr register. 0 nbs when high, the narrowband signal ha s been detected in the sin/sout path and when low, the narrowband signal has not been detected in the sin/sout path. bit name description register table 3 - line echo canceller control register (lec) (continued) external read/write address: 01 h reset value: 00 h 76543210 shft asc- nlp- inj- hpf- hclr adapt- ecby external read address: 22 h reset value: 00 h 76543210 - acmund hwlng - nlpdc dt nb nbs
zl38001 data sheet 33 zarlink semiconductor inc. register table 5 - line echo ca nceller status register (lsr) (* do not write to this register) bit name description 7 - reserved. 6- 5- 4- 3 nlpc when high, nlp is activated and when low nlp is not activated. 2 dt when high, double-talk is detected and when low double-talk is not detected. 1 nb this bit indicates a logical-or of status bits nbr + nbs (from asr register). 0 nbr when high, a narrowband signal has been detected in the receive (rin) path. when low no narrowband signal is not detected in the rin path. external read address: 02 h reset value: 00 h 76543210
zl38001 data sheet 34 zarlink semiconductor inc. register table 6 - receive gain control register bit name description 7 reserved must keep as logic 0. 6 reserved must keep as logic 1. 5 reserved must keep as logic 1. 4-0 g4-0 user gain control on the rin/rout path (tolerance of gains: +/- 0.15 db). the hexadecimal number represents g3 to g0 value in the table below. external read/write address:20 h reset value: 6d h 76543210 - - - g4 g3 g2 g1 g0 register value gain register value gain 0h -24 db 10h +24 db 1h -21 db 11h +27 db 2h -18 db 12h +30 db 3h -15 db 13h +33 db 4h -12 db 14h +36 db 5h -9 db 15h +39 db 6h -6 db 16h +42 db 7h -3 db 17h +45 db 8h 0db 18h +48db 9h +3 db 19h reserved ah +6 db 1ah reserved bh +9 db 1bh reserved ch +12 db 1ch reserved dh +15 db 1dh reserved eh +18 db 1eh reserved fh +21 db 1fh reserved
zl38001 data sheet 35 zarlink semiconductor inc. register table 7 - double talk gain control register 1 (dtgcr1) register table 8 - double talk gain control register 2 (dtgcr2) bit name description 7 - reserved. must keep as 0. 6 - reserved. must keep as 0. 5 - reserved. must keep as 1. 4 dtrgain this bit controls the gain level at r out during double talk. when this bit is high 12 db of attenuation is injected into the rout path during double talk. when this bit is low the gain pad is disabled. 3 - reserved. must keep as 0. 2 - reserved. must keep as 1. 1 - reserved. must keep as 0. 0 - reserved. must keep as 1. bit name description 7 - reserved. must keep as 0. 6 - reserved. must keep as 0. 5 - reserved. must keep as 0. 4 dtsgain this bit controls the gain level at sout during double talk. when this bit is high 12 db of attenuation is injected into the sout path during double talk. when this bit is low the gain pad is disabled. 3 - reserved. must keep as 0. 2 - reserved. must keep as 0. 1 - reserved. must keep as 0. 0 - reserved. must keep as 0. external read/write address: 32 h reset value: 25 h 76543210 hg 2 hg 1 hg 0 dtgain---- external read/write address: 12 h reset value: 00 h 76543210 ---dtsgain --
zl38001 data sheet 36 zarlink semiconductor inc. register table 9 - double talk detection threshold register (dtdt) register table 10 - receive (rin) peak detect register 1 (ripd1) bit name description 7dtdt 2 6dtdt 1 5dtdt 0 4 - reserved. must keep as 0. 3 - reserved. must keep as 0. 2 - reserved. must keep as 0. 1 - reserved. must keep as 0. 0 - reserved. must keep as 1. bit name description 7ripd 7 these peak detector registers allow the user to monitor the receive in signal (rin) peak level at reference point r1 (s ee figure 1). the information is in 16- bit 2?s complement linear coded format presented in two 8- bit registers. the high byte is in register 2 and the low byte is in register 1. 6ripd 6 5ripd 5 4ripd 4 3ripd 3 2ripd 2 1ripd 1 0ripd 0 external read/write address: 31 h reset value: 21 h 76543210 dtdt 2 dtdt 1 dtdt 0 ----- dtdt 2, dtdt 1, dtdt 0 value dtdt dtdt 2, dtdt 1, dtdt 0 value dtdt 000 -12 db 100 +12 db 001 -6db 101 +18db 010 0 db 110 +24 db 011 +6db 111 +30db external read address: 16 h reset value: 00 h 76543210 ripd 7 ripd 6 ripd 5 ripd 4 ripd 3 ripd 2 ripd 1 ripd 0
zl38001 data sheet 37 zarlink semiconductor inc. register table 11 - receive (rin) peak detect register 2 (ripd2) register table 12 - receive (rin) error peak detect register 1 (repd1) bit name description 7ripd 15 these peak detector registers allow the user to monitor the receive in signal (rin) peak level at reference point r1 (s ee figure 1). the information is in 16- bit 2?s complement linear coded format presented in two 8- bit registers. the high byte is in register 2 and the low byte is in register 1. 6ripd 14 5ripd 13 4ripd 12 3ripd 11 2ripd 10 1ripd 9 0ripd 8 bit name description 7repd 7 these peak detector registers allow the user to monitor the error signal peak level at reference point r2 (see figure 1). the information is in 16-bit 2?s complement linear coded format presente d in two 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6repd 6 5repd 5 4repd 4 3repd 3 2repd 2 1repd 1 0repd 0 external read address: 17 h reset value: 00 h 76543210 ripd 15 ripd 14 ripd 13 ripd 12 ripd 11 ripd 10 ripd 9 ripd 8 external read address: 18 h reset value: 00 h 76543210 repd 7 repd 6 repd 5 repd 4 repd 3 repd 2 repd 1 repd 0
zl38001 data sheet 38 zarlink semiconductor inc. register table 13 - receive (rin) error peak detect register 2 (repd2) register table 14 - receive (rout) peak detect register 1 (ropd1) bit name description 7 repd 15 these peak detector registers allow the user to monitor the error signal peak level at reference point r2 (see figure 1). the information is in 16-bit 2?s complement linear coded format presente d in two 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6 repd 14 5 repd 13 4 repd 12 3 repd 11 2 repd 10 1repd 9 0repd 8 bit name description 7ropd 7 these peak detector registers allow the user to monitor the receive out signal (rout) peak level at reference point r3 (see figure 1). the information is in 16-bit 2?s complement linear coded fo rmat presented in tw o 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6ropd 6 5ropd 5 4ropd 4 3ropd 3 2ropd 2 1ropd 1 0ropd 0 external read address: 19 h reset value: 00 h 76543210 repd 15 repd 14 repd 13 repd 12 repd 11 repd 10 repd 9 repd 8 external read address: 3a h reset value: 00 h 76543210 ropd 7 ropd 6 ropd 5 ropd 4 ropd 3 ropd 2 ropd 1 ropd 0
zl38001 data sheet 39 zarlink semiconductor inc. register table 15 - receive (rout) peak detect register 2 (ropd2) register table 16 - send (sin) peak detect register 1 (sipd1) bit name description 7ropd 15 these peak detector registers allow the user to monitor the receive out signal (rout) peak level at reference point r3 (see figure 1). the information is in 16-bit 2?s complement linear coded fo rmat presented in tw o 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6ropd 14 5ropd 13 4ropd 12 3ropd 11 2ropd 10 1ropd 9 0ropd 8 bit name description 7sipd 7 these peak detector registers allow the user to monitor the receive in signal (sin) peak level at reference point s1 (s ee figure 1). the information is in 16- bit 2?s complement linear coded format presented in two 8- bit registers. the high byte is in register 2 and the low byte is in register 1. 6sipd 6 5sipd 5 4sipd 4 3sipd 3 2sipd 2 1sipd 1 0sipd 0 external read address: 3b h reset value: 00 h 76543210 ropd 15 ropd 14 ropd 13 ropd 12 ropd 11 ropd 10 ropd 9 ropd 8 external read address: 36 h reset value: 00 h 76543210 sipd 7 sipd 6 sipd 5 sipd 4 sipd 3 sipd 2 sipd 1 sipd 0
zl38001 data sheet 40 zarlink semiconductor inc. register table 17 - send (sin) peak detect register 2 (sipd2) register table 18 - send error peak detect register 1 (sepd1) bit name description 7sipd 15 these peak detector registers allow the user to monitor the receive in signal (sin) peak level at reference point s1 (s ee figure 1). the information is in 16- bit 2?s complement linear coded format presented in two 8- bit registers. the high byte is in register 2 and the low byte is in register 1. 6sipd 14 5sipd 113 4sipd 12 3sipd 11 2sipd 10 1sipd 9 0sipd 8 bit name description 7 sepd 7 these peak detector registers allow the user to monitor the error signal peak level in the send path at reference point s2 (see figure 1). the information is in 16-bit 2?s complement linear coded format presented in two 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6 sepd 6 5 sepd 5 4 sepd 4 3 sepd 3 2 sepd 2 1 sepd 1 0 sepd 0 external read address: 37 h reset value: 00 h 76543210 sipd 15 sipd 14 sipd 13 sipd 12 sipd 11 sipd 10 sipd 9 sipd 8 external read address: 38 h reset value: 00 h 76543210 sepd 7 sepd 6 sepd 5 sepd 4 sepd 3 sepd 2 sepd 1 sepd 0
zl38001 data sheet 41 zarlink semiconductor inc. register table 19 - send error peak detect register 2 (sepd2) register table 20 - send (sout) peak detect register 1 (sopd1) bit name description 7 sepd 15 these peak detector registers allow the user to monitor the error signal peak level in the send path at reference point s2 (see figure 1). the information is in 16-bit 2?s complement linear coded format presented in two 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6 sepd 14 5 sepd 13 4 sepd 12 3sepd 11 2 sepd 10 1 sepd 9 0 sepd 8 bit name description 7sopd 7 these peak detector registers allow the user to monitor the send out signal (sout) peak level at reference point s3 (see figure 1). the information is in 16-bit 2?s complement linear coded fo rmat presented in tw o 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6sopd 6 5sopd 5 4sopd 4 3sopd 3 2sopd 2 1sopd 1 0sopd 0 external read address: 39 h reset value: 00 h 76543210 sepd 15 sepd 14 sepd 13 sepd 12 sepd 11 sepd 10 sepd 9 sepd 8 external read address: 1a h reset value: 00 h 76543210 sopd 7 sopd 6 sopd 5 sopd 4 sopd 3 sopd 2 sopd 1 sopd 0
zl38001 data sheet 42 zarlink semiconductor inc. register table 21 - send (sout) peak detect register 2 (sopd2) register table 22 - rout limiter register 1 (rl1) bit name description 7sopd 15 these peak detector registers allow the user to monitor the send out signal (sout) peak level at reference point s3 (see figure 1). the information is in 16-bit 2?s complement linear coded fo rmat presented in tw o 8-bit registers. the high byte is in register 2 and the low byte is in register 1. 6sopd 14 5sopd 13 4sopd 12 3sopd 11 2sopd 10 1sopd 9 0sopd 8 bit name description 7l 0 this bit is used in conjunction with rout limiter register 2. (see description below.) 6 - reserved 5- 4- 3- 2- 1- 0- external read address: 1b h reset value: 00 h 76543210 sopd 15 sopd 14 sopd 13 sopd 12 sopd 11 sopd 10 sopd 9 sopd 8 external read address: 24 h reset value: 80 h 76543210 l 0 ------ -
zl38001 data sheet 43 zarlink semiconductor inc. register table 23 - rout limiter register 2 (rl2) register table 24 - sout limiter register (sl) bit name description 7l 8 in conjunction with bit 7 ( l 0 ) of the above (rl1) register, this register (rl2) allows the user to program the output limiter threshold value in the rout path. default value is (07d)h which is equal to 3.14 dbmo maximum value is (1ff)h = 15 dbmo minimum value is (001)h = -38 dbmo 6l 7 5l 6 4l 5 3l 4 2l 3 1l 2 0l 1 bit name description 7l 4 this register allows the us er to program the output limiter threshold value in the rout path. default value is (1d)h which is equal to 3.14 dbmo maximum value is (1f)h 6l 3 5l 2 4l 1 3l 0 2 - reserved. must be keep as 1. 1 - reserved. must be keep as 0. 0 - reserved. must be keep as 1. external read address: 25 h reset value: 3e h 76543210 l 8 l 7 l 6 l 5 l 4 l 3 l 2 l 1 external read address: 26 h reset value: 3d h 76543210 l 4 l 3 l 2 l 1 l 0
zl38001 data sheet 44 zarlink semiconductor inc. register table 25 - firmware revision code register (frc) register table 26 - bootload ram control register (brc) bit name description 7frc 2 revision code of the firmware progra m currently being r un (default=rom=00). 6frc 1 5frc 0 4 - reserved 3- 2- 1- 0- bit name description 7 - reserved 6- 5- 4- 3c 3 ram_romb bit. when high, device ex ecutes from ram. when low, device executes from rom. 2c 2 boot bit. when high, puts device in bootload mode. when low, bootload is disabled. 1c 1 reserved. must be set to zero. 0c 0 reserved. must be set to zero. external read address: 03 h reset value: 00 h 76543210 frc 2 frc 1 frc 0 ----- external read address: 3f h reset value: 00 h 76543210 ---- c 3 c 2 c 1 c 0
zl38001 data sheet 45 zarlink semiconductor inc. register table 27 - bootload ram signature register (sig) bit name description 7sig 7 this register provides the signature of the bootloaded data to verify error-free delivery into the device. note: this register is only accessi ble if boot bit is high (bootload mode enabled) in the above brc register. whil e bootload is disabl ed, the register value is held constant at its reset seed value of ffh. 6sig 6 5sig 5 4sig 4 3sig 3 2sig 2 1sig 1 0sig 0 external read address: 07 h reset value: 10 h 76543210 sig 7 sig 6 sig 5 sig 4 sig 3 sig 2 sig 1 sig 0
previous package codes package code acn date issue apprd. c zarlink semiconductor 200 4 . all rights reserved.

acn date apprd. c zarlink semiconductor 2003 all rights reserved. issue previous package codes package code
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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